1. Field of the Invention
This invention relates to the field of Field Programmable Gate Arrays (FPGAs). More particularly, it relates to a method and apparatus for improving the efficiency of FPGAs by inclusion of programmable dedicated multi-bit output functional blocks within FPGAs.
2. The Prior Art
FPGAs comprise a multitude of FPGA logic modules (the smallest programmable functional blocks on an FPGA) which in turn comprise a plurality of FPGA gates. FPGAs are user programmed to carry out desired functions. Examples of FPGAs are described in U.S. Pat. No. 4,758,745 to Elgamal et al. and U.S. Pat. No. 4,870,302 to Freeman, both of which are hereby incorporated herein by reference as if set forth fully herein.
Logic modules of FPGAs generally comprise multi-bit input, single-bit output devices which are programmable to create any desired output from a given input. This is accomplished in the prior art with multiplexer structures, look-up tables and logic gates, Logic modules are generally not programmable on the fly but are usually programmed by the user in a substantially permanent way.
While FPGAs present an excellent and extremely flexible method of dealing with the processing of various digital signals, a relatively large number of FPGA logic modules are typically required in order to fashion such typical multi-bit functional blocks as adders, subtracters, magnitude comparators, identity comparators, up/down counters, registers, and multi-bit AND gates. Typically, several of these functional blocks are used for every few thousand FPGA gates. Using current technology, this can require a great number of FPGA modules to be dedicated to providing the functionality of these predictably required functional blocks.
There are two major drawbacks to building these functional blocks out of FPGA logic modules: first, it uses more surface area or "real estate" on the chip than is absolutely necessary; second, the performance of functional blocks built out of FPGA logic modules is much lower than the performance of even corresponding ASIC standard cells configured to do the same thing.
Another method of providing the functionality of the aforementioned functional blocks is to provide some additional distributed capability which resides in each of (or at least in a large number of) the individual FPGA logic modules. These enhancements can then be combined with the basic capabilities of the FPGA logic module itself to construct functional blocks which deliver higher performance in a smaller area than permitted by simply configuring standard FPGA modules to perform these functions. The drawback here is that the added distributed capability is purchased at the cost of reduced flexibility and freedom available to the placement and routing programs which likely will reduce the performance of other portions of the FPGA. Examples of such approaches are found in the carry chain feature incorporated in the XC-4000 products of Xilinx, Inc. of San Jose, Calif. and the EPM-7000 product of Altera Corporation, of San Jose, Calif.